Flat panel displays based on amorphous silicon thin film transistors (TFT) and liquid crystals (TFT-LC displays) are of great commercial importance, having captured a substantial portion of the flat-screen television and computer display markets. To reduce manufacturing costs and improve yields, in-process testing (IPT) is a critical component of the manufacturing process. It is highly desirable that the majority of defects within the TFT circuitry are identified (and, if possible, corrected) prior to the expensive steps that follow (filling with liquid crystal, alignment of the color filter glass, and addition of driver circuitry, etc.). Furthermore, there is increasing demand that all completed displays are entirely free of pixel defects. Reliable testing and repair of the TFT array is the preferred approach for achieving such a goal.
A method of testing TFT arrays is one in which the columns (TFT data lines) and rows (TFT gate lines) of the array are temporarily shorted in some fashion to a set of probe pads via bus circuitry that occupies space between TFT arrays. For example, every second gate line within several TFT panels on a common glass substrate (base plate) is wired to a common bus (gate even bus) and the alternate gate lines are wired to a second common bus (gate odd bus). Similarly, the alternate data lines are wired to a pair of common buses (data even and data odd buses). The bus lines and their associated contact probe pads occupy space between the individual TFT arrays (i.e. displays) manufactured in parallel on a single base substrate, and are removed when the individual arrays are scribed for final assembly of the displays. The aforementioned wiring arrangement enables the TFT arrays to be driven according to certain spatial and temporal patterns, such as a blinking checkerboard pattern, that can be imaged and analyzed for the purposes of fault detection.